AITIA's 100 Gb/s PCS/PMA and MAC FPGA core


  • IEEE 802.3ba-2010 full compliant implementation
  • Source code available for further development!
  • Uses Xilinx Virtex 6 device specific GTH transceivers, can be easily ported to other devices too
  • 512bit/320bit Receive/Transmit MAC data-interface running at 312,5Mhz
  • Optimized ethernet CRC checksum calculation on Rx and Tx MAC interfaces
  • Tested on C-GEP 100 with CFP SR optical modules
  • Simple and parameterizable traffic generator application available
  • Sample application with 100 Gb/s partitioned ISE project for fast development runtime, and guaranteed timing compliance.

100 Gb/s bps PCS/PMA+MAC IP Core